1. Field of the Invention
The present invention relates to a power amplifier formed using a BiFET process. More specifically, the present invention relates to a power amplifier capable of suppressing leakage current without increasing chip areas and manufacturing costs.
2. Background Art
Since a conventional GaAs-FET power amplifier has negative threshold voltage, it had a disadvantage that a negative gate bias voltage was required. On the other hand, a GaAs-HBT (hetero junction bipolar transistor) power amplifier does not require negative gate bias voltage, enables single power source operation, and has more even bias characteristics than the FET type. In recent years, therefore, a GaAs-HBT power amplifier has been actively used in mobile telephones such as CDMA or wireless LANs.
Recently, a Bi-FET process for forming a FET on the same substrate for a GaAs-HBT has been increasingly applied to products. Normally, in the case of a GaAs-based Bi-FET process, in addition to a HBT and depletion mode (normally ON) FET is mounted. Furthermore, in the academic conference (IEEE Radio Frequency Integrated Circuits Symposium 2008), a process for fabricating an enhancement-mode FET (normally OFF) on the same substrate in addition to a HBT and a depletion mode FET was reported.
In the Bi-FET power amplifier for mobile telephones, the mounting of ON/OFF functions (enable functions) by an enable voltage has been increasingly standardized. Such a power amplifier had a problem wherein if the threshold voltage of a depletion mode FET is varied, the reference voltage and the collector current is significantly varied. In general, the amplitude of an idle current (a bias current in the state wherein RF input power is absent) in a power amplifier determines the amplitude of linear gain. Therefore, the depression of gain variation due to process variation is one of important issues in designing. The reduction of enable voltage is also required.
In order to solve these problems, a reference voltage generating circuit, wherein the gain variation due to process variation is suppressed, has been proposed (for example, refer to FIG. 1 in Japanese Patent Application Laid-Open No. 2010-124408). Furthermore, a reference voltage generating circuit, wherein the ON voltage of the enable voltage using a depletion mode FET has also been proposed (for example, refer to FIG. 3 in Japanese Patent Application Laid-Open No. 2010-124408).